SF_OR_INTEN=SF_OR_INTEN_0, REDGE=REDGE_0, EOF_INT_EN=EOF_INT_EN_0, INV_PCLK=INV_PCLK_0, PrP_IF_EN=PrP_IF_EN_0, COF_INT_EN=COF_INT_EN_0, SWAP16_EN=SWAP16_EN_0, RXFF_INTEN=RXFF_INTEN_0, FCC=FCC_0, PACK_DIR=PACK_DIR_0, PIXEL_BIT=PIXEL_BIT_0, EXT_VSYNC=EXT_VSYNC_0, SOF_INTEN=SOF_INTEN_0, CCIR_MODE=CCIR_MODE_0, CCIR_EN=CCIR_EN_0, SFF_DMA_DONE_INTEN=SFF_DMA_DONE_INTEN_0, FB2_DMA_DONE_INTEN=FB2_DMA_DONE_INTEN_0, RF_OR_INTEN=RF_OR_INTEN_0, STATFF_INTEN=STATFF_INTEN_0, GCLK_MODE=GCLK_MODE_0, FB1_DMA_DONE_INTEN=FB1_DMA_DONE_INTEN_0, INV_DATA=INV_DATA_0, HSYNC_POL=HSYNC_POL_0, SOF_POL=SOF_POL_0
CSI Control Register 1
| PIXEL_BIT | Pixel Bit 0 (PIXEL_BIT_0): 8-bit data for each pixel 1 (PIXEL_BIT_1): 10-bit data for each pixel |
| REDGE | Valid Pixel Clock Edge Select 0 (REDGE_0): Pixel data is latched at the falling edge of CSI_PIXCLK 1 (REDGE_1): Pixel data is latched at the rising edge of CSI_PIXCLK |
| INV_PCLK | Invert Pixel Clock Input 0 (INV_PCLK_0): CSI_PIXCLK is directly applied to internal circuitry 1 (INV_PCLK_1): CSI_PIXCLK is inverted before applied to internal circuitry |
| INV_DATA | Invert Data Input. This bit enables or disables internal inverters on the data lines. 0 (INV_DATA_0): CSI_D[7:0] data lines are directly applied to internal circuitry 1 (INV_DATA_1): CSI_D[7:0] data lines are inverted before applied to internal circuitry |
| GCLK_MODE | Gated Clock Mode Enable 0 (GCLK_MODE_0): Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. 1 (GCLK_MODE_1): Gated clock mode. Pixel clock signal is valid only when HSYNC is active. |
| CLR_RXFIFO | Asynchronous RXFIFO Clear |
| CLR_STATFIFO | Asynchronous STATFIFO Clear |
| PACK_DIR | Data Packing Direction 0 (PACK_DIR_0): Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. 1 (PACK_DIR_1): Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. |
| FCC | FIFO Clear Control 0 (FCC_0): Asynchronous FIFO clear is selected. 1 (FCC_1): Synchronous FIFO clear is selected. |
| CCIR_EN | CCIR656 Interface Enable 0 (CCIR_EN_0): Traditional interface is selected. Timing interface logic is used to latch data. 1 (CCIR_EN_1): CCIR656 interface is selected. |
| HSYNC_POL | HSYNC Polarity Select 0 (HSYNC_POL_0): HSYNC is active low 1 (HSYNC_POL_1): HSYNC is active high |
| SOF_INTEN | Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. 0 (SOF_INTEN_0): SOF interrupt disable 1 (SOF_INTEN_1): SOF interrupt enable |
| SOF_POL | SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. 0 (SOF_POL_0): SOF interrupt is generated on SOF falling edge 1 (SOF_POL_1): SOF interrupt is generated on SOF rising edge |
| RXFF_INTEN | RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt. 0 (RXFF_INTEN_0): RxFIFO full interrupt disable 1 (RXFF_INTEN_1): RxFIFO full interrupt enable |
| FB1_DMA_DONE_INTEN | Frame Buffer1 DMA Transfer Done Interrupt Enable 0 (FB1_DMA_DONE_INTEN_0): Frame Buffer1 DMA Transfer Done interrupt disable 1 (FB1_DMA_DONE_INTEN_1): Frame Buffer1 DMA Transfer Done interrupt enable |
| FB2_DMA_DONE_INTEN | Frame Buffer2 DMA Transfer Done Interrupt Enable 0 (FB2_DMA_DONE_INTEN_0): Frame Buffer2 DMA Transfer Done interrupt disable 1 (FB2_DMA_DONE_INTEN_1): Frame Buffer2 DMA Transfer Done interrupt enable |
| STATFF_INTEN | STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt. 0 (STATFF_INTEN_0): STATFIFO full interrupt disable 1 (STATFF_INTEN_1): STATFIFO full interrupt enable |
| SFF_DMA_DONE_INTEN | STATFIFO DMA Transfer Done Interrupt Enable 0 (SFF_DMA_DONE_INTEN_0): STATFIFO DMA Transfer Done interrupt disable 1 (SFF_DMA_DONE_INTEN_1): STATFIFO DMA Transfer Done interrupt enable |
| RF_OR_INTEN | RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. 0 (RF_OR_INTEN_0): RxFIFO overrun interrupt is disabled 1 (RF_OR_INTEN_1): RxFIFO overrun interrupt is enabled |
| SF_OR_INTEN | STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt. 0 (SF_OR_INTEN_0): STATFIFO overrun interrupt is disabled 1 (SF_OR_INTEN_1): STATFIFO overrun interrupt is enabled |
| COF_INT_EN | Change Of Image Field (COF) Interrupt Enable 0 (COF_INT_EN_0): COF interrupt is disabled 1 (COF_INT_EN_1): COF interrupt is enabled |
| CCIR_MODE | CCIR Mode Select 0 (CCIR_MODE_0): Progressive mode is selected 1 (CCIR_MODE_1): Interlace mode is selected |
| PrP_IF_EN | CSI-PrP Interface Enable 0 (PrP_IF_EN_0): CSI to PrP bus is disabled 1 (PrP_IF_EN_1): CSI to PrP bus is enabled |
| EOF_INT_EN | End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. 0 (EOF_INT_EN_0): EOF interrupt is disabled. 1 (EOF_INT_EN_1): EOF interrupt is generated when RX count value is reached. |
| EXT_VSYNC | External VSYNC Enable 0 (EXT_VSYNC_0): Internal VSYNC mode 1 (EXT_VSYNC_1): External VSYNC mode |
| SWAP16_EN | SWAP 16-Bit Enable 0 (SWAP16_EN_0): Disable swapping 1 (SWAP16_EN_1): Enable swapping |